This invention relates to circuits for interfacing high frequency signals to logic levels and in particular, but not exclusively, to interfacing high frequency signals to ECL (emitter-coupled logic) logic levels and to an ECL clock drive circuit.
The conventional way to interface a high frequency sine wave to ECL logic levels is to use feedback around an inverting gate 1 (FIG. 1) to provide the required V.sub.BB d.c. bias of the input to the inverting gate. The resistor R terminates an input coaxial cable 2, whilst the choke L prevents high frequency loop gain and the resistor R.sub.f damps any tendency to oscillate at low frequency. The disadvantage of this configuration is that the input impedance is far from ideal, due to the choke L in the feedback path, particularly for use in transmission systems operating above 100 Mbits/sec.